To achieve increased density and performance of VLSI (very large scale integrated circuits) integrated circuits, the characteristic size of features on those circuits is decreased. Fabrication of IC devices with features smaller than 0.18 .mu.m, particularly fabrication of STI (shallow trench isolation) features, introduces new challenges in process development and control.
The process of making STI trenches typically involves a photolithographic step for patterning features in a photoresist layer overlying a silicon nitride (Si.sub.3 N.sub.4) layer on a silicon substrate. In this process, dark and bright field features, i.e. thin lines and narrow spaces between structures or lines, are formed at the same time. As the characteristic size of lines and spaces becomes smaller, the acceptable tolerance in feature size variation also becomes smaller.
Variation in the width of the lines and spaces produced in the photoresist layer depends on the photolithographic process conditions, depth of focus and exposure, and on the variation in thickness of the photoresist and underlying silicon nitride layer. However, the lines and spaces do not respond in the same way to the process conditions. While these variations did not present a problem for older devices with larger feature sizes, for 0.18 .mu.m scale devices, even with photoresist and Si.sub.3 N.sub.4 layer thickness variation kept to a practical minimum, the overlap in optimized process conditions to produce dark and bright field feature variations within acceptable tolerances is vanishingly small. Consequently, at the 0.18 .mu.m scale, the photolithographic process may not be readily manufacturable.
The problem with variation in Si.sub.3 N.sub.4 thickness is that it leads to variation in substrate reflectivity which, in turn, results in line width variation. A typical stack formed in patterning an isolation structure is shown in FIG. 1a where a patterned photoresist mask 22 overlays a Si.sub.3 N.sub.4 layer 18 in which a mask pattern is to be formed. An SiO.sub.2 layer 14 is between the Si.sub.3 N.sub.4 layer 18 and the silicon substrate 10. One solution to limiting line width variation is to introduce an organic anti-reflective coating (ARC) 20 between the photoresist and Si.sub.3 N.sub.4 18 layers to control substrate reflectivity, as shown in FIG. 1b. However, there are contamination and defect problems associated with organic ARC's. Furthermore, organic ARC's significantly increase processing complexity because they require etching and stripping steps separate from those for Si.sub.3 N.sub.4 layers.
What is needed is a way to minimize line width variation to provide a manufacturable photolithographic process at the 0.18 .mu.m scale without significantly increasing process complexity.